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10gbps active back-match, differential laser diode driver preliminary technical data ADN2525 rev. pr. e july 2004 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features up to 10.7gbps operation very low power: icc=157ma typical 24 ps rise/fall times pecl/cml compatible data inputs bias current range: 10ma to 100ma differential modulation current range: 10ma to 80ma automatic laser shutdown (als) 3.3v operation compact 3x3mm lfcsp package voltageCinput control for bi as and modulation currents xfp compliant bias current monitor applications sonet oc-192 optical transceivers sdh stm-64 optical transceivers 10gb ethernet optical transceivers xfp/x2/xenpak/msa 300 optical modules general description the ADN2525 laser diode driver is designed for direct modulation of packaged laser diodes having a differential impedance ranging from 5 ? to 50 ? . the active back- termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. the small package provide the optimum solution for compact modules where laser diodes are packaged in low pin-count optical sub-assemblies. the differential data inputs are pecl/cml compatible and terminated with an internal 100 ? differential resistor to minimize signal reflections to the data signal source. the modulation and bias currents are programmable via mset and bset control pins. by driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed loop control, and look-up tables. the automatic laser shutdown featur e allows the user to turn the bias and modulation currents on/off by driving the als pin with the proper logic levels. the product is available in a space saving 3mm 3mm lfcsp package specified from C40 0 c to 85 0 c. 50 ? imod 2 ? 200 ? 800 ? gnd vcc 50 ? 50 ? 200 ? 200 ? 800 ? 2 ? vcc vcc datap datan mset gnd bset ibmon ibias imodp imodn ADN2525 vcc als figure 1. functional block diagram
ADN2525 rev. pr. e | page 2 of 15 ADN2525-specifications ( vcc= vcc min to vcc max , t a = -40 0 c to 85 0 c, 50 ? differential load impedance, unless otherwise noted. typical values are specified at 25 0 c, imod=40ma ) table 1. parameter min typ max unit test conditions/comments bias current(ibias) bias current range 10 100 ma bias current while als asserted 100 a als=high compliance voltage C see note 1 0.6 vcc-0.8 v ibias=100ma 0.6 vcc-1.2 v ibias=10ma modulation current (imodp, imodn) modulation current range 10 80 ma diff. r load = 5 ? to 50 ? differential modulation current while als asserted 0.5 ma diff als=high rise time (20% to 80%) C see notes 2, 6 24 34 ps fall time (20% to 80%) C see notes 2, 6 24 34 ps pulse width distortion C see note 6 tbd tbd tbd ps overshoot C see notes 2, 6 tbd tbd % undershoot C see notes 2, 6 tbd tbd % random jitter C see notes 2 ,6 0.4 tbd ps rms deterministic jitter C see notes 3, 6 7.2 tbd ps p-p differential |s 22 | ?10 db f<10ghz, z 0 =50 ? differential compliance voltage C see note 1 vcc-1.1 vcc+1.1 v data inputs (datap, datan) input data rate 10.7 gbps nrz differential input swing 0.4 1.6 v p-p diff. differential ac coupled differential |s 11 | -10 db f<10ghz, z 0 =100 ? differential input termination resistance 85 100 115 ? differential bias control input (bset) bset voltage to ibias gain 80 100 120 ma/v bset input resistance 800 1000 1200 ? modulation control input (mset) mset voltage to imod gain 70 88 110 ma/v mset input resistance 800 1000 1200 ? bias monitor (ibmon) ibmon to ibias ratio 10 a/ma accuracy of ibias to ibmon ratio -3.5 +3.5 % 10ma ibias< 40ma, r ibmon =1k ? -2.5 +2.5 % 40ma ibias< 70ma, r ibmon =1k ? -2 +2 % 70ma ibias< 100ma, r ibmon =1k ? automatic laser shutdown (als) v ih 2.4 v v il 0.8 v i il -20 20 a i ih 0 200 a als assert time C see figure 2 10 s rising edge of als to fall of ibias and imod below 10% of nominal als negate time C see figure 2 10 s falling edge of als to rise of ibias and imod above 90% of nominal power supply v cc 3.07 3.3 3.53 v i cc C see note 4 31 38 ma v bset =v mset =0v isupply C see note 5 157 176 ma v bset =v mset =0v notes: 1. refers to the voltage between the pin for whic h the compliance voltage is specified and gnd. 2. the pattern used is composed by a repetitive sequence of 8 ones followed by 8 zeros at 10.7gbps rate. 3 the pattern used is k28.5 (00111110101100000101) at 10.7gbps rate. 4.only includes current in ADN2525 vcc pins. 5. includes current in ADN2525 vcc pins and dc current in imodp and imodn pull-up inductors. see section on power consumption for total supply current calculation. 6. measured using the high-speed characterization circuit shown in figure 3.
ADN2525 rev. pr. e | page 3 of 15 90% 10% als ibias &imod als assert time als negate time t t figure 2. als timing diagram mset nc1 als gnd bset ibmon ibias gnd vcc datap datan vcc vcc imodp imodn vcc j2 j3 10nf 10nf gnd gnd gnd j8 10nf vee tp1 10nf` vee ADN2525 vee z 0 =25 ? z 0 =25 ? gnd gnd z 0 =50 ? z 0 =50 ? gnd gnd 10 ? gnd j5 gnd 22 f vee z 0 =50 ? z 0 =50 ? gnd gnd gnd gnd gnd gnd gnd gnd gnd bias tee bias tee gnd gnd 50 ? 50 ? oscilloscope 70 ? 35 ? 35 ? tp2 vee bias tee: picosecond pulse labs model 5542-219 adaptor: pasternack pe-9436 2.92mm female-to-female adaptor attenuator:pasternack pe-7046 2.92mm 20db attenuator adaptor adaptor attenuator attenuator vmset + - vbset - + z 0 =50 ? z 0 =50 ? 1k ? vee figure 3. high-speed characterization circuit
ADN2525 rev. pr. e | page 4 of 15 absolute maximum ratings table 2. parameter min max units conditions/comments supply voltage C vcc to gnd -0.3 4.2 v imodp, imodn to gnd vcc-1.5 4.75 v datap, datan to gnd vcc-1.8 vcc-0.4 v all other pins -0.3 vcc+0.3 v junction temperature 150 0 c storage temperature -65 150 0 c soldering temperature 240 0 c less than 10sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational section of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal specifications table 3. parameter min typ max units conditions/comments j-top 2.6 5.8 10.7 0 c/w thermal resistance from junction to top of package j-pad 65 72.2 79.4 0 c/w thermal resistance from juncti on to bottom of exposed pad esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADN2525 rev. pr. e | page 5 of 15 typical performance characteristics(ta=25 0 c,vcc=3.3v) 23.00 23.50 24.00 24.50 25.00 25.50 26.00 26.50 27.00 27.50 28.00 0 20406080100 differential modulation curent(ma) r i s e t i m e ( p s ) figure 4. rise time vs. imod 23.00 23.50 24.00 24.50 25.00 25.50 26.00 26.50 27.00 27.50 0 20406080100 differential modulation current(ma) f a l l t i m e ( p s ) figure 5. fall time vs. imod 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 020406080100 differential modulation current(ma) r a n d o m j i t t e r ( p s ) figure 6 random jitter vs. imod 0 1 2 3 4 5 6 7 8 9 0 20406080100 differential modulation current(ma) d e t e r m i n i s t i c j i t t e r ( p s ) figure 7. deterministic jitter vs. imod 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 0 20406080100 differential modulation current(ma) t o t a l s u p p l y c u r r e n t ( m a ) ibias=10ma ibias=50ma ibias=100ma figure 8. total supply current vs. imod all caps (initial c ap) 000 000 000 000 000 000 000 a l l c a p s ( i n i t i a l c a p ) 000 000 000 000 000 tbd figure 9. differential |s11|
ADN2525 rev. pr. e | page 6 of 15 all caps (initial c ap) 000 000 000 000 000 000 000 a l l c a p s ( i n i t i a l c a p ) 000 000 000 000 000 tbd figure 10. differential |s22| 26 26.5 27 27.5 28 28.5 29 29.5 30 30.5 31 2 1 4 6 8 9 10 11 12 rise time (ps) count 7 5 3 figure 11. worst case rise time distribution (vcc=3.07v, ibias=100ma, imod=80ma, t a =85 0 c) 26 26.5 27 27.5 28 28.5 29 29.5 30 30.5 31 2 1 4 6 8 9 10 11 12 fall time (ps) count 7 5 3 13 figure 12. worst case fall time distribution (vcc=3.07v, ibias=100ma, imod=80ma, t a =85 0 c) figure 13. electrical eye diagram (sonet oc192, prbs31, imod=80ma) figure 14. filtered sonet oc192 optical eye diagram (prbs31 pattern, pav=-2dbm, er=7db, 17% mask margin, nec nx8341uj tosa) figure 15. filtered 10g ethernet op tical eye (prbs31 pattern, pav=- 2dbm, er=5db, 41% mask margin, diagram nec nx8341uj tosa)
ADN2525 rev. pr. e | page 7 of 15 pin configuration and fu nction descriptions pin 1 indicator to p view ADN2525 nc = no connect mse t nc als gnd v c c i m o d n i m o d p v c c v c c d a t a p d a t a n v c c bset ibmon ibias gnd 1 2 3 4 9 10 11 12 5 6 7 8 1 3 1 4 1 5 1 6 figure 16. pin configuration note: there is an exposed pad on the bottom of the package that must be connected to the vcc or gnd plane with filled vias. table 4. pin function descriptions pin no. mnemonic i/o description 1 mset input modulation current control input 2 nc n/a no connect C leave floating 3 als input automatic laser shutdown 4 gnd power negative power supply 5 vcc power positive power supply 6 imodn output modulation current negative output 7 imodp output modulation current positive output 8 vcc power positive power supply 9 gnd power negative power supply 10 ibias output bias current output 11 ibmon output bias curre nt monitoring output 12 bset input bias current control input 13 vcc power positive power supply 14 datap input data si gnal positive input 15 datan input data si gnal negative input 16 vcc power positive power supply exposed pad pad power connect to gnd or vcc
ADN2525 rev. pr. e | page 8 of 15 theory of operation general as shown in figure 1, the ADN2525 consists of an input stage, and two voltage controlled current sources for bias and modulation. the bias current is available at the ibias pin, and also can be monitored at ibmon pin. the mset voltage is converted to current. this current is applied to a differential pair that switches current into two internal resistors according to the data signal applied to the driver. the voltage generated across these resistors is applied to the output stage circuitry, which produces the differential modulation current that drives the laser. this output stage also implements the active back- match circuitry for proper transmission line matching and power consumption reduction. the ADN2525 can drive a load having differential impedance ranging from 5 ? to 50 ? . input stage the input stage of the ADN2525 converts the data signal applied to the datap and datan pins to a level that ensures proper operation of the high-speed switch. the equivalent circuit of the input stage is shown in figure 17. vcc 50 ? 50 ? vcc vcc datap datan figure 17. equivalent circuit of the input stage the datap and datan pins are terminated internally with a 100 ? differential termination resistor to minimize signal reflections at the input that could otherwise lead to degradation in the output eye diagram. the 100 ? resistor is built as a combination of two 50 ? resistors for each data pin connected to a common mode voltage source that is biasing the input stage transistors. note that it is not recommended to drive the ADN2525 with single-ended data signal sources. the ADN2525 input stage must be ac-coupled with the signal source to eliminate the need for matching between the common mode voltages of the data signal source and the input stage of the driver (see figure 18). the ac-coupling capacitors should be chosen so that their impedance is less than 50 ? over the required frequency range. generally this is achieved using capacitor values from 10nf to 100nf. ADN2525 datap datan c c 50 ? 50 ? data signal source figure 18. ac-coupling the data source to the ADN2525 data inputs bias current the bias current is generated internally using a voltage to current converter, consisting of an internal operational amplifier and a transistor as shown in figure 19. gnd 200 ? 200 ? 800 ? 2 ? vcc ibmon ibias bset i bmon i bias ADN2525 figure 19. voltage to current converter used to generate ibias the voltage to current conversion factor is set at 100ma/v by the internal resistors. the bias current is monitored using a current mirror with a gain equal to 1/100, given by the ratio of the degeneration resistors (2 ? /200 ? ). the current mirror output is the ibmon pin that sources the ibias/100 current from vcc. by connecting a resistor between ibmon and gnd, the bias current can be monitored as a voltage across the resistor. a low temperature coefficient, precision resistor must be used for the ibmon resistor (r ibmon ). any error in the value of r ibmon due to tolerances or drift in its value over temperature,
ADN2525 rev. pr. e | page 9 of 15 contributes to the overall error budget for the ibias monitor voltage. if the ibmon voltage is being connected to an adc for a/d conversion, r ibmon should be placed close to the adc to minimize errors due to voltage drops on the ground plane. the equivalent circuits of the bset, ibias and ibmon pins are shown in figures 20, 21 and 22. 200 ? v cc bset v cc 800 ? figure 20. equivalent circuit of the bset pin 2 ? 2k ? v cc 100 ? v cc ibia s figure 21. equivalent ci rcuit of the ibias pin 100 ? vcc 500 ? vcc ibmon vcc figure 22. equivalent ci rcuit of the ibmon pin the recommended configuration for bset, ibias and ibmon is shown in figure 23. ADN2525 bset vbset gnd ibmon ibias 1k to laser cathode l r ibmon + - ibias figure 23 recommended configuration for bset, ibias and ibmon pins the circuit used to drive the bset voltage must be capable of driving the 1k ? input resistance of the bset pin. for proper operation of the bias current source, the voltage at ibias pin must be between the compliance voltage specifications for this pin (see page 2) over supply, temperature and bias current range. the maximum compliance voltage is specified on page 2 for only two bias current levels (10ma and 100ma) but it can be calculated for any bias current using the following formula: v compliance (v)=vcc (v)-0.75-4.4 ibias(a) the function of the inductor l is to isolate the capacitance of the ibias output from the high frequency signal path. automatc laser shutdown (als) the als pin is a digital input that enables/disables both the bias and modulation currents depending on the logic state applied (see table 5). table 5 als logic state ibias and imod high disabled low enabled floating enabled the als pin is compatible with 3.3v cmos and ttl logic levels. its equivalent circuit is shown in figure 24.
ADN2525 rev. pr. e | page 10 of 15 100 ? vcc 2k ? vcc als 50k ? figure 24. equivalent circuit of the als pin modulaton current the modulation current can be controlled by applying a dc voltage to the mset pin. this voltage is converted into a dc current using a voltage to current converter using an operational amplifier and a bipolar transistor as shown in figure 25. 50 ? imod 2 ? 200 ? 800 ? from input stage vcc mset gnd imodp imodn ADN2525 figure 25. generation of modulation current on ADN2525 this dc current is used as a tail current for the differential pair that generates a high-speed voltage across the resistive loads based on the data signal applied to the input stage (datap and datan pins). the high-speed differential voltage is applied to the output stage circuitry that generates the differential modulation current available at the imodp and imodn pins. the equivalent circuits for mset, imodp and imodn are shown in figures 26 and 27. the output stage also generates the active back termination, which provides proper transmission line termination. active back termination uses feedback around an active circuit to synthesize a broadband termination resistance. this provides excellent transmission line termination, while dissipating less power than a traditional resistor passive back termination. 200 ? vcc mset vcc 800 ? figure 26. equivalent ci rcuit of the mset pin vcc vcc 3.3 ? 3.3 ? 330 ? 330 ? imodn imodp figure 27. equivalent circuit of the imodp and imodn pins the recommended configuration of the mset, imodp and imodn pins is shown in figure 28. ADN2525 mset vmset gnd imodn imodp l vcc l vcc z 0 =25 ? z 0 =25 ? c c load vcc l l ibias + ? z 0 =25 ? z 0 =25 ? figure 28. recommended configuration for mset, imodp and imodn pins
ADN2525 rev. pr. e | page 11 of 15 the ratio between the voltage applied to the mset pin and the differential modulation current available at the imodp and imodn pins is a function of the load impedance value as shown in figure 29. msetvoltagetoimodgainvs.differentialload resistance 80 90 100 110 120 130 140 150 160 170 180 0 5 10 15 20 25 30 35 40 45 50 55 diffe rential load resistance m a / v figure 29. mset voltage to modulation current ratio vs. differential load impedance knowing the resistance of the tosa, the user can calculate the voltage range that should be applied to the mset pin to generate the required modulation current range. the circuit used to drive the mset voltage must be capable of driving the 1k ? resistance of the mset pin. in order to be able to drive 80ma modulation currents through the differential load the output stage of the ADN2525 (imodp, imodn pins) must be ac-coupled to the load. the voltage at these pins will have a dc component equal to vcc and an ac component with single-ended peak-to-peak amplitude of imod 25 ? . this is the case even if the load impedance is less than 50 ? differential, since the transmission line characteristic impedance sets the peak-to-peak amplitude. for normal operation, the voltages at the imodp and imodn pins must be within the range shown in figure 30. the user must perform headroom calculations to ensure that the voltages at imodp and imodn pins are within the normal operation region for the required modulation currents. due to its excellent s22 performance the ADN2525 can drive differential loads that range from 5 ? to 50 ? . in practice many tosas have differential resistance less than 50 ?. in this case, with 50 ? differential transmission lines connecting the ADN2525 to the load, the load end of the transmission lines will be mis-terminated. this mis-termination leads to signal reflections back to the driver. the excellent back-termination in the ADN2525 absorbs these reflections, preventing their re- reflection back to the load. this enables excellent optical eye quality to be achieved, even when the load end of the transmission lines is significantly mis-terminated. the connection between the load and the ADN2525 must be made with 50 ? differential (25 ? single-ended) transmission lines so that the driver end of the transmission lines is properly terminated. v imodp, imodn vcc vcc-1.1v vcc+1.1v normal operation region figure 30. allowable range for the voltage at imodp and imodn power consumption the power dissipated by the ADN2525 is given by ibias v i 5 . 13 v vcc p ibias ply sup mset + ? ? ? ? ? ? ? ? + = where, vcc= power supply voltage ibias= the bias current generated by the ADN2525 v mset = the voltage applied to the mset pin i supply = the sum of the current that flows into the vcc, imodp and imodn pins of the ADN2525 when ibiias=imod=0 expressed in amps (see table 1). v ibias =the average voltage on ibias pin considering v bset /ibias=10 as the conversion factor from v bset to ibias, the dissipated power becomes: ibias bset ply sup mset v 10 v i 5 . 13 v vcc p + ? ? ? ? ? ? ? ? + = to ensure long-term reliable operation, the junction temperature of the ADN2525 must not exceed 125 0 c. for improved heat dissipation the modules case can be used as heat sink as shown in figure 31. a compact optical module is a complex thermal environment, and calculations of device junction temperature using the package j-a (junction-to- ambient thermal resistance) do not yield accurate results.
ADN2525 rev. pr. e | page 12 of 15 t to p t j t pad die package thermal compound module case pcb filled vias copper plane thermo-couple figure 31. typical optical module structure the following procedure can be used to estimate the ic junction temperature. t top = temperature at top of package in 0 c. t pad = temperature at package exposed paddle in 0 c. t j = ic junction temperature in 0 c. p = power disipation in w. j-top = thermal resistance from ic junction to package top. j-pad = thermal resistance from ic junction to package exposed pad. j-pad p j-top t pad t pad t top t top t j fig. 32. electrical model for thermal calculations t top and t pad can be determined by measuring the temperature at points inside the module, as shown in fig. 30. the thermo- couples should be positioned so as to obtain an accurate measurement of the package top and paddle temperatures. using this model the junction temperature can be calculated using the formula: top j pad j top j pad pad j top top j pad j j t t p t ? ? ? ? ? ? + + + = ) ( where j-top and j-pad are given in table 3 and p is the power dissipated by the ADN2525 .
ADN2525 rev. pr. e | page 13 of 15 applications information typical application circuit figure 33 shows the typical application circuit for the ADN2525. the dc voltages applied to the bset and mset pins control the bias and modulation currents. the bias current can be monitored as a voltage drop across the 1k resistor connected between the ibmon pin and gnd. the als pin allows the user to turn on/off the bias and modulation currents depending on the logic level applied to the pin. the data signal source must be connected to the datap and datan pins of the ADN2525 using 50 ? impedance transmission lines. the modulation current outputs imodp and imodn must be connected to the load (tosa) using 50 ? differential (25 ? single-ended) impedance transmission lines. the rf interface between the ADN2525 and the tosa must be designed to ensure high quality optical eyes. for more details on how to choose the components from the rf interfacing circuitry please contact the factory mset nc1 als gnd bset ibmon ibias gnd vcc datap datan vcc vcc imodp imodn vcc datap datan c1 c2 mset als c6 10nf bset vcc tp1 1k c5 10nf ADN2525 z 0 =25 ? z 0 =25 ? gnd gnd +3.3v gnd 20 f vcc z 0 =50 ? z 0 =50 ? gnd gnd gnd vcc vcc vcc vcc vcc z 0 =25 ? z 0 =25 ? vcc tosa c3 c4 l1 l3 l6 l7 vcc vcc c7 l2 l4 l5 l8 r1 r2 r3 r4 r5 figure 33. typical ADN2525 application circuit pcb layout guidelines due to the high frequencies at which the ADN2525 operates, care should be taken when designing the pcb layout in order to obtain optimum performance. it is recommended to use controlled impedance transmission lines for the high-speed signal paths the length of the tr ansmission lines must be kept to a minimum to reduce losses and pattern dependant jitter. the pcb layout must be symmetrical to ensure the balance between the differential inputs/outputs of the ADN2525. all the vcc and gnd pins must be connected to solid copper planes using low inductance connections. when the connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. each gnd pin must be locally decoupled with high quality capacitors. if proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each gnd pin. a 20 f tantalum capacitor must be used as general decoupling capacitor for the entire module the exposed pad should be connected to the vcc or gnd plane using filled vias so that solder does not leak through the vias during reflow. using filled vias under the package greatly enhances the reliability of the connectivity of the exposed pad to the gnd plane during reflow.
ADN2525 rev. pr. e | page 14 of 15 design example this section describes a design example that covers the followings: ? headroom calculations for ibias, imodp and imodn pins ? calculation of the typical voltage required at bset and mset pins in order to get the desired bias and modulation currents this design example assumes that the impedance of the tosa is equal to 25 ? , the forward voltage of the laser at low current is v f =1v, ibias=40ma, imod=60ma, and vcc=3.3v headroom calculations the headroom calculations must be performed for ibias, imodp and imodn. the ADN2525 will work within the datasheet specifications if the voltages at the above mentioned pins are within the datasheet specifications (see page 2, bias current and modulation current sections). considering the typical application circuit shown in figure 33 the voltage at the ibias pin can be written as: 4 l 3 l tosa f ibias v v ) z ibias ( v vcc v ? ? ? ? = where, vcc= supply voltage v f = the forward voltage across the laser at low current z tosa = the impedance of the tosa v l3 , v l4 = the dc voltage drop across l3 and l4 for proper operation the minimum voltage at the ibias pin should be greater than 0.6v. assuming that the voltage drop across the 25 ? transmission lines is negligible and v l3 =v l3 =0v, v f =1v, ibias=40ma v ibias =3.3-1-(0.04 25)=1.3v >0.6v the maximum voltage at the ibias pin must satisfy the condition: 2.53v ) a ( ibias 44 . 0 75 . 0 vcc v max ibias = ? ? < v ibias =1.3v <2.53v for headroom calculations at the modulation current pins (imodp, imodn) the voltage has a dc component equal to vcc due to the ac-coupled configuration and a swing equal to imod 25 ? . for normal operation of the ADN2525 the voltage at each modulation output pin should be within the normal operating region shown in figure 27. assuming the voltage drop across l1 and l2=0v and imod=60ma, the minimum voltage at the modulation output pins is equal to: vcc-(imod 25 ? )/2=vcc-0.75 >vcc-1.1v the maximum voltage at the modulation output pins is equal to: vcc+(imod 25 ? )/2=vcc+0.75 >vcc+1.1v bset and mset pin voltage calculation in order to get the desired bias and modulation current the bset and mset pins of the ADN2525 must be driven with the appropriate dc voltage. the bset voltage range required at the bset pin to generate the required ibias range can be calculated using the ibias/v bset ratio specified on page 2 of this datasheet. assuming ibias=40ma, the typical ibias/v bset ratio of 100ma/v, the bset voltage is given by the formula: v 4 . 0 100 40 v / ma 100 ) ma ( ibias v bset = = = the bset voltage range can be calculated using the required ibias range, and the minimum and maximum ibias/v ibias values specified in table 1. the voltage required at the mset pin in order to get the desired modulation current can be calculated using the formula: k imod v mset = where k is the mset voltage to imod ratio. the value of k is dependant on the actual impedance of the tosa and it can be read using the plot shown in figure 28. for an impedance of the tosa of 25 ? , k=120ma/v. using the formula shown above, the voltage required at the mset pin in order to generate 60ma modulation current is 0.5v. the mset voltage range can be calculated using the required imod range, and the minimum and maximum k values. these can be obtained from the following formulae: k 88 110 k k 88 70 k max min = =
ADN2525 rev. pr. e | page 15 of 15 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq 1.65 1.50 sq * 1.35 bottom view 16 5 13 8 9 12 4 * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension figure 34. 16-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package descri ption package option lead finish ADN2525acpz-wp -40c to +85c 16-lfcsp, 50pc waffle pack cp-16 lead-free ADN2525acpz-500rl7 -40c to +85c 16-lfcsp, 500pc reel cp-16 lead-free ADN2525acpz-reel7 -40c to +85c 16-lfcsp, 7 1500pc reel cp-16 lead-free

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